1. Field of the Invention
The present invention relates to a demodulation circuit of an optical disc apparatus and, more particularly, to a demodulation circuit which performs an FSK demodulation on a reproduced signal of an optical disc apparatus which reproduces information recorded on a recordable optical disc.
Additionally, the present invention relates to a decode circuit of an optical disc apparatus and, more particularly, to a decode circuit which decodes a reproduced BIDATA signal to obtain ATIP data in an optical disc apparatus which regenerates information recorded on a recordable optical disc.
The present invention also relates to a digital PLL circuit which generates a clock signal synchronous with pulses having a predetermined pulse width included in an input signal.
2. Description of the Related Art
Conventionally, there is a recordable compact disc system (CD-R) which uses a recordable optical disc. The CD-R system records synchronization information and address information as a wobble signal for controlling rotation of the disc by forming wobbling or meandering grooves on the CD-R.
The wobble signal is a signal which is FSK modulated by a modulation signal BIDATA of a biphase code which is information regarding addresses on a disc. When the disc is rotated at a specified linear velocity, a WBL frequency fwbl is 22.05.+-.1 KHz. The ATIP signal includes a synchronization signal (ATIPsyc) which is information regarding the addresses, addresses and an error detection code CRC. The frequency of the synchronization signal is 75 Hz.
FIG. 1 shows an example of a demodulation circuit which obtains the modulation signal BIDATA by FSK demodulating the wobble signal reproduced from an optical disc.
In FIG.1, a wobble signal input to a terminal 1 is supplied to a phase comparator 2, and the wobble signal is subjected to a phase comparison with an output signal of a VCO (voltage-controlled oscillator) 3. The phase error signal obtained by the phase comparator 2 is supplied to a low-pass filter (LPF) 4 so as to eliminate an unnecessary high-frequency component therefrom. The filtered phase error signal is output from a terminal 5 as an FSK demodulation signal, and also is supplied to a multiplier 6. The signal is multiplied by a loop gain K by the multiplier 6, and is supplied to the VCO 14.
In an analog circuit, when an entire circuit is integrated into a single semiconductor device, it is difficult to accurately set circuit element constants. Thus, circuit elements requiring accuracy must be externally mounted, resulting in a problem in that integration is difficult.
Additionally, a digital circuit may be used to enable integration of the circuit. In this case, the wobble signal is binarized so as to generate a WBL signal, and an edge interval of the thus obtained WBL signal is measured so as to perform an FSK demodulation. However, a quality of the wobble signal may be influenced by a quality of a reproducing circuit. Especially, if a noise influencing the phase of the wobble signal enters, there is a problem in that the quality of the demodulation signal is deteriorated.
Conventionally, the signal BIDATA is supplied to a PLL circuit so as to generate a PLL clock. A decode circuit latches the signal BIDATA by an edge of the PLL signal so as to decode the ATIP data.
However, when an S/N ratio of the wobble signal is decreased or if there is a defect on the optical disc, the position of the edge of the signal BIDATA is influenced and is fluctuated. In such a case, an error may be generated in the ATIP data which is latched by the edge of the PLL clock. Such an error can be detected by an error detection code CRC provided in the ATIP data, but the error cannot be corrected. Thus, there is a problem in that quality of the ATIP information is deteriorated.
FIG.2 is a block diagram of an example of a conventional analog PLL (phase-locked loop) circuit. In the figure, an input signal including a predetermined frequency component is input to a terminal 10, and is supplied to a phase comparator 11. The phase comparator 11 performs a phase comparison on the input signal and a signal having a predetermined frequency supplied by a frequency divider 14 so as to generate a phase error signal. The phase error signal is supplied to a VCO (voltage-controlled oscillator) 13 via an LPF (low-pass filter) 12. An oscillation signal output by the VCO 13 is divided by a frequency divider 14 into a predetermined frequency component, and is output from a terminal 15 and also supplied to the phase comparator 11. Thereby, the VCO 13 generates an oscillation signal which is synchronous with the predetermined frequency component of the input signal, and the thus-obtained signal is output from the terminal 15.
FIG.3-(A) shows the signal BIDATA obtained by FSK-demodulating the WBL signal reproduced from a disc. The signal BIDATA is supplied to the PLL circuit shown in FIG.2 so as to generate a clock signal shown in FIG.3-(B). In the signal BIDATA, the repeated pulses having widths 1T and 2T represent addresses and CRC codes. The synchronization signal is represented by a pattern of pulses having widths 3T, 1T, 1T, 3T so as to differentiate the synchronization signal from the addresses and the CRC codes. It should be noted that, in the present specification, the width of the pulses refers to a duration of a high-level period or a low-level period.
The phase comparator 11 compares the phase of edges of the signal BIDATA and the clock signal shown in FIG.3-(A) and (B). Thus, the 75-Hz component of the synchronization signal enters the phase error signal, and the 75-Hz component cannot be eliminated by the LPF 12. Thus, there is a problem in that a stability of the clock signal is deteriorated.
In order to solve the above-mentioned problem, the applicant suggested in Japanese Laid-Open Patent Application No. 8-109655 a digital PLL circuit which comprises means for measuring an interval of edges of an input signal and means for generating a clock signal based on the interval of edges.
In the circuit suggested by the applicant, a width of a pulse (an interval of edges) of the signal BIDATA is measured by counting the system clock. It is determined whether the pulse width of the signal BIDATA corresponds to 1T, 2T or 3T by comparing the count value of threshold values of the pulse widths 1T and 2T with a counted value of the system clock. When the pulse width corresponds to 1T, the count value itself is selected; when the pulse width corresponds 2T, one half of the count value is selected; and when the pulse width corresponds to 3T, the immediately preceding count value is selected. The clock signal is generated based on the thus-selected count values. Accordingly, there is a problem in that a circuit scale is increased since a comparison circuit and a selection circuit for each of the widths 1T and 2T are used.
Additionally, in the optical disc apparatus, a spindle servo control is performed based on the clock signal generated in the above-mentioned digital PLL circuit so as to obtain a constant linear velocity of the optical disc. However, the clock signal cannot follow a rotation of the optical disc during a pull-in operation in which the linear velocity is not constant or during a track jump in which an optical pickup is moved in a radial direction of the optical disc since fixed values are used for the threshold values of the pulse widths 1T and 2T. Thus, there is a problem in that a stable spindle servo cannot be achieved.